Design Of Programmable Logic Arrays

Design Of Programmable Logic Arrays

Programmable logic arrays (PLAs) are digital electronic devices that can be programmed to perform specific logical functions. They consist of a grid of AND gates, which produce product terms when their inputs are high, and an array of OR gates, which sum the product terms to produce the output. The inputs and their complements are connected to the AND gates, and the outputs of the AND gates are connected to the inputs of the OR gates. The design of PLAs is critical to their performance and versatility. A good design of PLAs requires several criteria. First, it should have a modular structure, which facilitates the testing, verification, and modification of the device. Second, it should minimize the number of product terms and simplify the sum terms to reduce the number of logic gates and delay time. Third, it should use efficient algorithms to optimize the placement of the product terms in the array to achieve maximum coverage and minimize unused cells. Fourth, it should incorporate feedback paths from the outputs to the inputs to implement synchronous and asynchronous sequential circuits. Fifth, it should provide a flexible programming scheme that enables the user to program the device using various methods, such as fuse, anti-fuse, EEPROM, flash, or SRAM. To improve the performance of PLAs, designers can use several techniques. One of them is the use of multi-level logic minimization algorithms, such as Karnaugh maps or Quine-McCluskey method, to reduce the complexity of the sum terms. Another technique is the use of don’t cares, which represent the don’t-care outputs for some input combinations, to reduce the size of the sum terms and simplify the Boolean expression. A third technique is the use of precharge-evaluate logic, which speeds up the PLA operation by precharging the inputs before evaluating the logic function. A fourth technique is the use of testability features, such as scan chains or boundary scan, which simplify the testing and diagnosis of faults in the device.

Programmable logic arrays, AND gates, OR gates, modular structure, logic minimization, don’t cares, precharge-evaluate logic, testability features

— Joshua Wilson

CITATION : "Joshua Wilson. 'Design Of Programmable Logic Arrays.' Design+Encyclopedia. https://design-encyclopedia.com/define/design-of-programmable-logic-arrays?E=301299 (Accessed on October 14, 2026)"